Quad flat non-leaded package comprising a semiconductor device

ABSTRACT

A semiconductor package is proposed. The semiconductor package includes a discrete semiconductor chip on a die pad, a plurality of bond pads situated next to the chip and formed with a plurality of connecting mechanisms and an encapsulant for encapsulating the chip and the pads. In a preferred embodiment the die pad and/or the bond pads comprise means for vertically and laterally interlocking the pads to the encapsulant. The interlocking means of the bond pads and the die pad significantly enhance the bonding strength between the pads and the encapsulant for preventing delamination or cracking, so that quality and reliability of the quad flat non-leaded semiconductor package comprising a discrete can be assured.

The present invention generally relates to a quad flat non-leadedleadframe package structure for housing a semiconductor device. Moreparticularly, the present invention relates to a quad flat non-leadedleadframe package structure for housing a discrete semiconductor device.

One of the major trends in the semiconductor packaging industry is touse surface-mount technology (SMT) as a replacement for conventionalplated-through-hole (PTH) technology. SMT offers several distinctadvantages over PTH technology, such as greater packaging density,higher lead counts with shorter interconnection lengths and easierautomation. Since SMT requires electronic devices and components to bemountable on the surface of a printing wiring board, the materials andstructure of traditional leaded components including capacitors,resistors and inductors have to be redesigned to meet the modern-daydemand for short, thin, light and small electronic devices.

Examples of semiconductor devices accomplishing these objects include“Quad flat non-leaded (QFN)” packages. Quad flat non-leaded electronicdevices have a relatively new package structure, in whichspace-consuming outer leads protruding laterally out of a package areeliminated. Instead, external electrode pads to be electricallyconnected to a motherboard are provided on the backside of the QFNpackage.

A quad flat non-leaded package, especially a leadless leadframe package(LLP) makes use of a metal leadframe-type substrate structure in theformation of a chip scale package (CSP). In a typical leadless leadframepackage, a copper leadframe strip or panel is patterned by stamping oretching to define a plurality of arrays of chip substrate features. Eachchip substrate feature includes a die attach pad and a plurality ofcontacts (bonds) disposed about their associated die attach pad.

During assembly, dice are attached to the respective die attach pads andconventional wire bonding is used to electrically couple each die totheir associated bond pad contacts on the leadframe strip. After thewire bonding process, a synthetic resin cap is moulded over the topsurface of each array of wire-bonded dice. The dice are then singulatedand tested using conventional sawing and testing techniques.

The resulting packaged chip can then be surface mounted on a printedcircuit board or other substrate using conventional techniques.

It should be appreciated that during singulation, the only materialsholding the die pads and the bond pad contacts in place is the moldingmaterial. Due to lack of adequate support or clamping force duringsingulating the encapsulant, the die pad or the leads tend to bedislocated during singulation.

U.S.20020027273A1 discloses a semiconductor package that includes asemiconductor chip; a plurality of leads surrounding the chip and formedwith a plurality of connecting mechanisms and strengthening structures;and an encapsulant for encapsulating the chip and the leads. The leadshave the same height as the semiconductor package, allowing upper andlower surfaces of the leads to be exposed to the outside of theencapsulant, and further enhance the dissipation of heat generated bythe chip in operation. The strengthening structures of the leadssignificantly enhance the bonding strength between the leads and theencapsulant for preventing delamination or cracking, so that quality andreliability of the semiconductor package can be assured.

Such a leadless leadframe package, however, has the following drawbacks.The invention makes use of lead frames having a plurality of leadsextending inwardly from a frame of the lead frame, wherein the leads areformed with strengthening structures on sides thereof, and connectingmechanisms are on surfaces of inner sides of the leads. Such a leadframe structure is not suitable for commodity products such asindividually packaged discrete semiconductor devices.

It is therefore an object of the present invention to provide animproved quad flat non-leaded leadframe semiconductor package especiallyuseful for individually packaged discrete semiconductor devices.

Another object of the invention is to provide a quad flat non-leadedleadframe semiconductor package for improving the connection reliabilityat the time of packaging.

Yet another object of the invention is to provide a quad flat non-leadedleadframe semiconductor package intended to facilitate the processmanagement.

In accordance with the foregoing and other objectives, the quad flatnon-leaded semiconductor device proposed in the invention comprises:

-   -   a discrete semiconductor die;    -   a die pad having a first lateral surface for supporting the        discrete semiconductor die; and    -   a plurality of vertical surfaces that are perpendicular to the        first lateral surface, at least one bond pad having a first        lateral surface and a plurality of vertical surfaces that are        perpendicular to the first lateral surface;    -   at least one bond wire for connecting the discrete semiconductor        die to the bond pad; and    -   an encapsulant for encapsulating the die, die pad, bond wire and        bond pad having lateral and vertical outer surfaces, wherein the        die pad is disposed at the perimeter of the encapsulant and        partially exposed to one vertical outer surface of the        encapsulant.

In one embodiment of the invention, a vertical surface of the die pad isprovided with interlocking means.

In a preferred embodiment of the invention, a vertical surface of thedie pad is provided with means for interlocking the die pad verticallyand laterally.

In another preferred embodiment of the invention, a first and a secondvertical surface of at least one die pad is provided with interlockingmeans.

In still another embodiment of the invention, a vertical surface of abond pad is provided with interlocking means.

These and other features and advantages of the present invention will beapparent to those skilled in the art from the following detaileddescription and drawings.

FIG. 1 shows two options for process steps to be performed formanufacturing a QFN package comprising discrete semiconductor devices.

FIG. 2 is a plan view of a leadframe for QFN packages comprising 1944discretes.

FIG. 3 is a plan view of die pads and bond pads according to anembodiment of the invention.

FIG. 4 shows a cross-sectional view illustrating interlocking means ofdie pads and bond pads according to one embodiment of the invention.

FIG. 5 is a perspective view of the QFN package according to oneembodiment of the invention.

A quad flat non-leaded semiconductor package 10, as illustrated in FIG.5, includes the following members:

-   -   a semiconductor chip 11;    -   a die pad 12 having a base body with a first lateral face 12 a        for attaching the chip 11, a second lateral face 12 b exposed to        the outside of the encapsulant for external electrical        connections and vertical faces 12 c, 12 d;    -   two bond pads 13 disposed next to the die pad 12 and        electrically connected to the chip 11; and    -   an encapsulant 19 for encapsulating the chip 11, the die pad 12,        and the bond pads 13. The bond pads 13 each have a first lateral        face 13 a, a second lateral face 13 b which is exposed to the        outside of the encapsulant 19 for external electrical        connections, and is coplanar with the second lateral face of the        die pad 12 b. The second lateral faces of die pad and bond pad        12 b, 13 b may serve as I/O terminals for electronic        transmission so as to electrically connect the semiconductor        package 10 to a substrate such as an external printed circuit        board (not shown).

The package furthermore comprises a plurality of bond wires 14, eachbond wire being connected between a conductive contact on the discretesemiconductor die and a first surface of a bond pad.

The package furthermore comprises an encapsulant material 19, whichforms a package body.

The package has a polyhedral shape with peripheral side faces and edges.One lateral peripheral face comprises the second lateral faces of diepads and bond pads.

The package has a perimeter, and the discrete semiconductor device isplaced at the perimeter of the package. At least one vertical face ofthe die pad is at least partially exposed to an external surface of thepackage.

Two methods of manufacturing a Quad Flat Non-leaded Leadframe Packageare shown in FIG. 1. For making a Quad Flat Non-leaded Leadframe Packageuse is made of a metal lead frame. Such a metal frame may also include acoverlay. A plurality of die pads and bond pads is present within andconnected to the frame. Dice are attached to the respective die attachpads and conventional wire bonding is used to electrically couple eachdie to their associated bond pad contacts on the leadframe strip. Afteran encapsulation step comprising moulding and removing the coverlay, thedie pads and leads may be plated. Thereafter the die pads and bond padsare severed from the leadframe and completed packages are sawn from theleadframe. A plurality of packages, e.g. several thousand, may be madesimultaneously.

The discrete semiconductor device as used for the present invention ispreferably an active or passive discrete electronic device such as atransistor, diode, LED, resistor, capacitor and inductor incorporated ina chip (die).

A die pad is used for supporting the discrete semiconductor device chip(die) present thereon and disposed in a perimeter region of theencapsulant.

Such a die pad has a base body shaped as a polyhedron. The basic bodyshape is usually derived from a cuboid and will be described as such inthe following. Yet it should be understood that the cuboid shape canhave deviations from the regular cuboid shape, e.g. recesses, groovesand other deviations.

The die pad has a first substantially planar lateral surface 12 a uponwhich a die 11 is placed during package assembly.

Opposite the first surface is a substantially planar second lateralsurface 12 b that is peripheral with regard to the surface of thepackage. The second lateral surface of the die pad 12 is located withinsubstantially the same plane as the lower surface of the resinencapsulant 19, and exposed without being covered with the resinencapsulant.

Furthermore, the die pad comprises a plurality of vertical faces,extending perpendicularly to the lateral faces. A first lateral surface12 d is peripheral with regard to the surface of the package. Accordingto the singulating technique used to singulate individual packages,first lateral face 12 d may be wholly or partially exposed to the outersurface of the package. For example, the first vertical side integrallyfaces an outside surface of the encapsulant or it has a lid pointing toan outer surface of the encapsulant.

In a preferred embodiment of the invention, at least one inner lateralface is provided with interlocking means, especially means for laterallyand vertically interlocking means for safely anchoring the die pad inthe encapsulant. Preferably interlocking means are provided to the rearface of the first lateral face.

Such interlocking means may comprise protrusions provided with surfacesthat have a re-entrant angle in one direction. Such protrusions thathave a re-entrant angle in one direction may comprise a circular lidbeing cantilevered to all vertical faces of the die pad.

In a preferred embodiment such interlocking means may compriseprotrusions provided with surfaces that have a re-entrant angle in atleast two directions.

Such protrusions having a re-entrant angle in at least two directionsmay comprise open-ended or closed trapezoids, dovetails, T-shapedprotrusions, anchor-shaped protrusions, horn-shaped protrusions or a lidpointing outwards to an inner surface of the encapsulant.

Protrusions need not be symmetrical—as in barb-shaped protrusions.

Such interlocking protrusions may have a stepped profile.

Protrusions on two sides may work together to laterally and verticallyinterlock the die pad into the encapsulant.

FIGS. 4 and 5 illustrate a die pad with interlocking means formed as adovetail.

As viewed from above, the inner rear surface of the die pad is arrangedlike a cantilever lip with a dovetail protrusion.

More specifically, the protrusion of the die pad protrudes inward, andthe first lateral surface of the die pad is greater in area than thesecond surface thereof. In FIG. 4, the hatched area indicates the devicearea, the cross-hatched regions indicate the half-etched portions of thedie pads (and bond pads).

Besides protrusions, grooves could also be contemplated as interlockingmeans. Such a groove surrounds the vertical faces and may be circular,rectangular or any other complex shape.

Also as shown in FIGS. 4 and 5, for example, at least longitudinalgrooves 16 running the full length, or part of the length, of the bodyperimeter edges might be useful.

Also, each of the bond pads 13 may be provided with interlocking meansto cushion the forces causing delamination.

Bond pads are used for electrically connecting the discretesemiconductor chip device (die) to outside electrodes.

Such bond pads have a polyhedron-shaped base body. The basic body shapeis usually derived from a cuboid and will be described as such in thefollowing. Yet it should be understood that the cuboid shape can havee.g. recesses, grooves and other deviations from the regular cuboidshape.

The bond pads have a first substantially planar lateral surface 13 aupon which bond wires 14 are placed during package assembly.

Opposite the first surface is a substantially planar second lateralsurface 13 b that is peripheral with regard to the surface of thepackage. The second lateral surface of the die pad 12 is located withinsubstantially the same plane as the lower surface of the resinencapsulant 19, and exposed without being covered with the resinencapsulant.

Furthermore, the bond pads comprise a plurality of vertical facesextending perpendicularly to the lateral faces. A first lateral surface13 d is peripheral with regard to the surface of the package. Accordingto the singulating technique used to singulate individual packages,first lateral face 13 d may be wholly or partially exposed to the outersurface of the package. For example, the first vertical side integrallyfaces an outside surface of the encapsulant or it has a lid pointingoutward to an outer surface of the encapsulant.

In a preferred embodiment of the invention, at least one inner lateralface of each bond pad is provided with interlocking means, especiallymeans for laterally and vertically interlocking means for safelyanchoring bond pads in the encapsulant. Preferably, interlocking meansare provided to the rear face of the first lateral face.

Such interlocking means may comprise protrusions provided with surfacesthat have a re-entrant angle in one direction. Such protrusions thathave a re-entrant angle in one direction may comprise a circular lidbeing cantilevered to all vertical faces of the bond pad.

In a preferred embodiment, such interlocking means may compriseprotrusions provided with surfaces that have a re-entrant angle in atleast two directions.

Such protrusions having a re-entrant angle in at least two directionsmay comprise open-ended or closed trapezoids, dovetails, T-shapedprotrusions, anchor-shaped protrusions, horn-shaped protrusions or a lidpointing outward to an inner surface of the encapsulant.

Protrusions need not be symmetrical such as, for example, in barb-shapedprotrusions.

Such interlocking protrusions may have a stepped profile.

Protrusions on two sides may work together to laterally and verticallyinterlock the bond pads into the encapsulant.

FIGS. 4 and 5 illustrate bond pads with interlocking means on twovertical faces formed as a V-angle.

As viewed from above, the inner rear surfaces of the bond pads arearranged like a cantilever lip with a V-shaped protrusion.

More specifically, the protrusion of the bond pads protrude inward, andthe first lateral surface of each bond pad is greater in area than thesecond surface thereof. In FIG. 4, the hatched area indicates the devicearea, the cross-hatched regions indicate the half-etched portions of thebond pads.

Besides protrusions, grooves could also be contemplated as interlockingmeans. Such a groove surrounds the vertical faces and may be circular,rectangular or of any other complex shape.

Also as shown in FIGS. 4 and 5, for example, at least longitudinalgrooves 16 running the full length, or part of the length, of the bodyperimeter edges might be useful.

The number, location and shapes shown in FIG. 3 for protrusions(interlocking means) 15 of leadframe 20 are exemplary only. The number,location and shape of the protrusions will vary according to theapplication. An advantage of the present invention is that theinterlocking means can be designed to accommodate the number andlocation of the die pads and bonding pad(s) of a particular discretesemiconductor die.

When the semiconductor chip is molded with a resin encapsulant afterhaving been bonded and fixed onto the protruding portion 6 of the diepad 1 with an adhesive, the resin encapsulant is received at theundercuts of interlocking means 15. Accordingly, undercut surfaces ofinterlocking means interact with the corresponding subfaces of theencapsulant for fixing the members mechanically to the relativesubsurface of the package. Thereby, the interlocking means prevent thedie pads and bond pads from being pulled vertically or laterally fromthe package body, thus preventing that the reliability of theresin-molded semiconductor device is adversely affected.

Discrete semiconductor chip dice 11 of a plurality of different sizescan be packaged on the die pad, and the contact area of thesemiconductor dice 11 and the die pad can be enlarged e.g. by a troughto improve the contact between the semiconductor die 2 and the die pad,thereby preventing the die pad and the semiconductor chip 11 from beingseparated.

The semiconductor die 11 may be bonded onto the central portion of thedie pad via a gluing process.

Thereafter the dice 11 are electrically connected to associated bondpads 13 with fine metal bond wires 14.

Bonding wires are typically made of gold. When gold bonding wires areused in combination with a copper substrate, it is advantageous to platecontact landings using silver (or another material) to improve theadhesion of the bonding wires to the landings.

After all of the dice have been wire bonded or otherwise electricallyconnected to the appropriate contact landings, one or more plastic caps21 are formed over the substrate panel 20 as illustrated in FIG. 1. Inthe described embodiment, a separate plastic cap is formed over alldevices of device areas 23. That is, four separate caps as outlined indashed lines in FIG. 2 a. However, it should be appreciated that asingle cap or a different number of caps can readily be provided.

In this case, since the bottoms of the die pad and bond pads are notcovered with the resin encapsulant 15, a “single-sidemolded structure”is obtained.

The die pad 12, bond pads 13, semiconductor chip 11 and fine metal wires14 are encapsulated within the resin encapsulant 19. However, therespective lower parts of the bond pads and die pads around the outerperiphery of the package protrude downward and sideward out of the lowersurface of the resin encapsulant 19. These lower parts of the padsfunction as external electrodes (or external terminals) to beelectrically connected to a motherboard.

Hereinafter, the effects attainable by the functions of a QFN packageaccording to the invention will be described.

The package of the present invention has numerous advantages, and isuseful in numerous applications for discrete electronic devices,including power devices. The package may be made small in size. Forexample, the packages may be near chip size. In addition, the packagesmay be very thin. Packages having thickness as low as about 0.5 mm orless can be fabricated according the present invention. In addition, thebond pads can be placed close to the die, minimizing the length of bondwires and improving electrical performance. The exposed second surfaceof the die pad and bond pads can be connected by metal solder to theprinted circuit board for package cooling.

No outer leads exist beside the bond pads and die pads. Instead, thelower part of each of these signal leads 1 functions as the externalelectrode. Accordingly, such a structure contributes to downsizing of apower QFN package without limiting the size of a semiconductor chipmounted. Moreover, since no resin burr exists on the respective lowersurfaces of the external electrodes, the electrodes of the motherboardcan be bonded to these external electrodes in a more reliable manner.

Furthermore, since the vertical faces of the pads may have interlockingmeans for laterally and vertically locking the pads to the encapsulant,pads can cushion the deforming force during machining of theencapsulant. Accordingly, it is possible to prevent the die pad 2 andthe bond pads from being deformed or displaced as a result of themachining forces.

It is a further advantage of the invention that tools designed for quadflat non-leaded packaging of integrated circuits can be used withoutmajor alterations being necessary.

Hereinafter, a method for manufacturing the QFN package comprising adiscrete semiconductor device according to the invention will bedescribed with reference to the accompanying drawings. FIGS. 1, 2 and 4illustrate respective process steps for manufacturing the QFN packageaccording to the first embodiment.

FIGS. 2A and 2B show a schematic plan view of a QFN matrix leadframe 20used for QFN fabrication; and FIG. 2C shows a schematic sectional viewof an unsingulated batch of package units constructed on the QFN matrixleadframe 20.

Referring initially to FIG. 2, a leadless leadframe 20 suitable for usein accordance with one embodiment of the present invention will bedescribed. As seen therein, a conductive panel 21 is provided that has aplurality of segments 22 each having a plurality of device areas 23 forthe individual package regions in a plurality of rows and a plurality ofcolumns formed thereon. In the embodiment shown, the conductive paneltakes the form of a leadframe strip having a one-dimensional array ofdevice segments. However, in alternative embodiments, conductive panelshaving a wide variety of different shapes and device area layouts may beprovided.

As shown in FIG. 4, the QFN matrix leadframe 20 is predefined with amatrix of package sites 23 used for the fabrication of a batch of QFNpackage units thereon. These package sites 23 are delimited from eachother by grid-like connecting means 24 formed along the borderlines ofthe package sites 23, and each include a die pad 12 and a plurality ofbond pads 13 which are all connected to the grid-like connect bar 24 sothat they can be held together before being singulated.

So, a great number of QFNs comprising discrete semiconductor devices canbe manufactured from one lead frame.

It has been found helpful to adhere an adhesive tape to the bottomsurface of the leadframe strip or panel 101 during the assembly process.The adhesive coverlay tape helps support the die pads and bond padsduring the die attach and wire bonding operations, and also preventsflash (i.e. unwanted plastic) from forming on the underside of theleadframe strip or panel 20 during the molding process.

The die pads and bond pads comprising interlocking means 15 as well assaw pits and saw notches 25 in the leadframe may be formed by anysuitable process. This is sometimes referred to as a half-etch orpartial etch process since the etch is intended to form troughs in thesubstrate rather than etch completely through the substrate panel 20. Awide variety of conventional etching techniques can be used tofacilitate the etching process.

As is well known, chemical etching (also known as chemical milling) is aprocess that uses photolithography, photoresist, and metal-dissolvingliquid chemicals to etch a pattern into a metal strip. Typically, alayer of photoresist is applied to one or both planar surfaces of thestrip. Next, the resist layer is exposed to light through a mask havinga desired pattern. The photoresist is then developed and cured, forminga patterned photoresist mask. Next, chemicals are sprayed or otherwiseapplied to one or both planar surfaces of the masked strip. The exposedportions of the strip are etched away, leaving the desired pattern inthe metal strip.

A two-step etching process is used to form leadframe 20 of FIGS. 2 and4. The first etching step serves to etch one or both planar surfaces ofthe strip according to a resist pattern applied onto one or both of theplanar surfaces of the strip. This first etching step etches completelythrough portions of the metal strip to form the overall pattern of theleadframe, as exemplified in FIG. 2. Next, a second resist pattern isformed on portions of one side of the leadframe. The interlocking meansof the die pad, bond pads and saw troughs are not covered by the secondresist pattern, and thus are susceptible to further etching. The secondetching step etches partially through the leadframe from one sideaccording to the second resist pattern. This second etch step forms therecessed surfaces of leadframe 20, e.g., interlocking means of die padand bond pads, shown as cross-hatched sections. Saw troughs typicallyare also subjected to this second etch step. When the chemicals haveetched a selected distance through the thickness of selected portions,the second etch step is stopped. In other words, the second etching stepetches partially through the thickness of selected portions of the diepad and bond pads. The amount of material etched away in this secondetching step is governed by the need to have a sufficient amount ofencapsulant material flow beneath the interlocking means of die pad andbond pads to secure die pad and bond pads to the package body.Typically, the second etching step removes about 50% of the thickness ofthe die pad and bond pads, but the amount removed may range from about33% to 75% of the thickness of the die pads and bond pads. Due toimperfections in the etch process, re-entrant angles may not beorthogonal, but rather only substantially orthogonal, and the etchedsidewalls of die pad and bond pad may not be planar, but rather possessradiused corners.

After the leadframe panel 20 has been patterned, it may optionally beplated with a material that facilitates better wire bonding. Theleadframe 20 may be plated with metal layers of nickel (Ni), palladium(Pd) and gold (Au), either at this point in time or after the mouldingprocess step.

After said optional plating of the die pads, discrete semiconductor dice11 are mounted on the die pads 12 using conventional die attachmenttechniques.

In the process step 2 shown in FIG. 1, the semiconductor chip 4 ismounted on the central portion of the die pad in the leadframe 20prepared and bonded by means of gluing with silver paste containing anepoxy resin as a binder. This process step is referred to as “diebonding”.

Then, in the process step 3 shown in FIG. 1, the electrode pads (notshown) of the discrete semiconductor chip 11 are electrically connectedto the bond pads 13 with the fine metal wires or an equivalent conductor14. This process step is referred to as “wire bonding”. The fine metalwires 14 may be made of an appropriately selected material such asaluminium (Al) or gold (Au).

After all of the dice have been wire bonded or otherwise electricallyconnected to the appropriate contact landings, one or more plastic caps22 are formed over the substrate panel 20 as illustrated in FIG. 2B. Inthe described embodiment, a separate plastic cap is formed over alldevices of each device area 23. That is, four separate caps as outlinedin dashed lines in FIG. 2A. However, it should be appreciated that asingle cap or a different number of caps can readily be provided.

In this case, since the bottoms of the die pad and bond pads are notcovered with the resin encapsulant 19, a “single-sidemolded structure”is obtained.

The caps 22 may be formed using any conventional molding processincluding transfer molding and injection molding. In the describedembodiment, a molded array-type transfer molding process is used.

Resin is applied over the top side of the lead frame in the region 22 soas to embed the semiconductor chips, pads and wires. Migration of resinto the underside of the lead frame 20 is prevented. The resin migratesinto the recesses 25 and is solidified during a curing process. Becauseof the configuration of the recesses 25, withdrawal of the solidifiedresin is prohibited. As a result, the solidified resin within therecesses 25 effectively becomes anchored to each of the devices.

After the caps 22 have been formed, the coverlay on the back surface ofthe substrate 20 is removed to expose the backside of bond pads and diepads as illustrated in FIG. 1. In step 5 the exposed surfaces of theleadframe, including the exposed second surfaces of the die pad andleads, one plated with a metal, such as copper, gold, lead-tin solder,tin, nickel, palladium, or any solderable metal. Depending on theapplication and the material used for making the leadframe, step 5 maybe omitted.

In step 6 a completed package is severed from the encapsulatedleadframe. In particular, step 6 obliterates the disposable portions ofthe leadframe and/or severs the disposable portions of the leadframe 24,such as the rectangular frame, from the non-disposable components of theleadframe, such as the die pad and leads. Depending on the encapsulationmethod used in step 4, step 6 also may cut the encapsulant material toform peripheral sides of the package.

Preferably a saw is used to cut lengthwise along the saw troughs (sawpits).

Orthogonal cuts are made to singulate individual semiconductor devices.

During the singulation process, a cutting blade of a fixed width W isused to cut into the QFN matrix leadframe 20 and the encapsulation body19 along the crosswise singulation lines and lengthwise singulationlines, for the purpose of singulating the combined batch of QFN packageunits constructed together on the QFN matrix leadframe 20 intoindividual ones. As further shown in FIG. 1, the cutting by the sawingblade is carried out all the way into the QFN matrix.

By performing this cutting process step, the end faces of the die padsand bond pads cut off are substantially flush with the side faces of theresin encapsulant 19. That is to say, this structure does not includeany outer leads, which are ordinarily provided as external terminals.Instead, solder ball electrodes may be provided for this structure asalternative external terminals under the external electrodes, which arerespective exposed lower parts of the bond pads and die pads that arenot covered with the resin encapsulant 19. In individual cases, a solderplating layer is sometimes formed in place of the solder balls.

1. A quad flat non-leaded semiconductor package device comprising: adiscrete semiconductor die; a die pad having a first lateral surface forsupporting the semiconductor die; and a plurality of vertical surfacesthat are perpendicular to the first lateral surface, at least one bondpad having a first lateral surface and a plurality of vertical surfacesthat are perpendicular to the first lateral surface; at least one bondwire for connecting the discrete semiconductor die to the bond pad; andan encapsulant for encapsulating the die, die pad, bond wire and bondpad having lateral and vertical outer surfaces, wherein the die pad isdisposed at the perimeter of the encapsulant and partially exposed toone vertical outer surface of the encapsulant.
 2. A quad flat non-leadedsemiconductor package device according to claim 1, wherein a verticalsurface of the die pad is provided with interlocking means.
 3. A quadflat non-leaded semiconductor package device according to claim 1,wherein a vertical surface of the die pad is provided with means forinterlocking the die pad vertically and laterally.
 4. A quad flatnon-leaded semiconductor package device according to claim 1, wherein afirst and a second vertical surface of at least one pad is provided withinterlocking means.
 5. A quad flat non-leaded semiconductor packagedevice according to claim 1, wherein a vertical surface of a bond pad isprovided with interlocking means.